Digital circuit designs often include counter circuitry to measure time between events by counting cycles of various clock signals or other signals in the circuit design. In complex digital systems, a real-time counter may be shared between different processing units to keep track of time. Such shared real-time counters often include highly accurate or high resolution clock signals that may be generated by a high accuracy crystal oscillator, for example.
High resolution clock signals and high accuracy crystal oscillators operate at very high frequencies and consume much more energy than lower resolution clock signals and lower accuracy oscillators operating at lower frequencies. To reduce energy consumption, digital circuits may be configured to shut off a high frequency clock signal during periods when a lower frequency clock signal is suitable for processing operations of the circuits.
Circuitry may be configured to switch certain clock signal inputs between a fast clock signal source and a slow clock signal source at various times to save energy. However, such switching between a fast clock signal and a slow clock signal can introduce inaccuracies to the output of a real-time counter that provides a count based on the switched clock signal. Therefore, systems that employ a slow clock signal during a low power mode commonly include two separate counters, a fast counter driven by the fast clock and a slow counter driven by the slow clock. When the low power mode is complete, simple arithmetic has been used based on the slow counter to advance the fast counter by the number of fast clock periods that would have passed during the low power mode. This dual-counter approach dis-advantageously involves the use of multiple counters and multiplication circuitry or software. Another disadvantage of the dual-counter approach is that a real-time count based on cycles of the fast clock may not be available during the low power mode.